收藏本站
BU9844GUL-W (16Kbit)
Datasheet
I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
I 2 C BUS communication
1. I 2 C BUS data communication
2
and acknowledge is always required after each byte.
I 2 C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and
serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by addresses peculiar to devices.
EEPROM becomes “slave”. And the device that outputs data to bys during data communication is called “transmitter”,
and the device that receives data is called “receiver “.
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
P
START ADDRESS R/W
ACK
DATA
ACK
DATA
ACK
STOP
condition
condition
Figure 30. Data transfer timing
2. Start condition (start bit recognition)
(1) Before executing each command, start condition (start bit) where SDA goes from “HIGH” down to “LOW” when SCL is
“HIGH” is necessary.
(2) This IC always detects whether SDA and SCL are in start condition (start bit) of not, therefore, unless this condition is
satisfied, any command is executed.
3. Stop condition (stop bit recognition)
(1) Each command can be ended by SDA rising from “LOW” to “HIGH” when stop condition (stop bit), namely, SCL is
“HIGH”.
4. Acknowledge (ACK) signal
(1) This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device ( μ -COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
(2) This device (this IC at slave address input of write command , read command , and μ -COM at data output of read
command) at the receiver (receiving) side sets SDA “LOW” during 9 clock cycles, and outputs acknowledge signal
(ACK signal) showing that it has received the 8bit data.
(3) This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) “LOW”.
(4) Each write action outputs acknowledge signal (ACK signal) “LOW”, at receiving 8bit data (word address and write
data).
(5) Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) “LOW”.
(6) When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master ( μ -COM) side, this
IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop condition (stop bit), and ends read action.
And this IC gets in standby status.
5. Device addressing
(1) Output slave address after start condition from master.
(2) The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to “1010”.
(3) Next slave addresses (P2 P1 P0) are upper 3bit of word address, put these and word address ( WA0 to WA7 )
together, 11bit word address ( 2048byte ) of the device specified.
(4) The most insignificant bit ( R / W --- READ / WRITE ) of slave address is used for designating write or read action, and
is as shown below.
Setting R / W to 0 --- write (setting 0 to word address setting of random read)
Setting R / W to 1 --- read
Type
Slave Address
Maximum number
of Connected Buses
BU9844GUL-W
1
0
1
0
P2 P1 P0 R / W
1
P0 to P2 are page select bits (Upper 3bit of word address) .
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
12/26
TSZ02201-0R2R0G100470-1-2
17.Sep.2013 Rev.002
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
BU9847GUL-WE2 IC EEPROM 4KBIT 2WIRE VCSP50L1
BU9880GUL-WE2 IC EEPROM 64KBIT 2WIRE VCSP50L1
BU9882FV-WE2 IC EEPROM 2KBIT 400KHZ 14SSOP
BU9883FV-WE2 IC EEPROM 6KBIT 400KHZ SSOP16
BU9889GUL-WE2 IC EEPROM 8KBIT 2WIRE VCSP50L1
BU9891GUL-WE2 IC EEPROM 4KBIT VCSP T/R
BU9897GUL-WE2 IC EEPROM SERIAL VCSP50L2
BU99901GUZ-WE2 IC EEPROM 32KBIT 2WIRE VCSP
相关代理商/技术参数
BU9847GUL-W 制造商:ROHM 制造商全称:Rohm 功能描述:WL-CSP EEPROM family I2C BUS
BU9847GUL-W_10 制造商:ROHM 制造商全称:Rohm 功能描述:WL-CSP EEPROM family I2C BUS
BU9847GUL-WE2 功能描述:电可擦除可编程只读存储器 电可擦除可编程只读存储器 Serial-2Wire 4Kb RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
BU98570CH-3BW 制造商:ROHM 制造商全称:Rohm 功能描述:65,536 Colors 98RGB x 70 STN LCD control driver
BU98582CH-3BW 制造商:ROHM 制造商全称:Rohm 功能描述:65,536 Colors 104RGB x 82 STN LCD control driver
BU98664CH-3BW 制造商:ROHM 制造商全称:Rohm 功能描述:65,536 Colors 132RGB x 164 STN LCD control driver
BU9873F-GTE2 功能描述:Real Time Clock (RTC) IC Clock/Calendar I2C, 2-Wire Serial 8-SOIC (0.173", 4.40mm Width) 制造商:rohm semiconductor 系列:- 包装:剪切带（CT） 零件状态:有效 类型:时钟/日历 特性:警报器，闰年 存储容量:- 时间格式:HH：MM：SS（12/24 小时） 日期格式:YY-MM-DD-dd 接口:I2C，2 线串口 电压 - 电源:1.8 V ~ 5.5 V 电压 - 电源，电池:- 电流 - 计时（最大）:1μA ~ 1.35μA @ 3V ~ 5.5V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.173"，4.40mm 宽） 供应商器件封装:8-SOP 标准包装:1
BU9873FJ-GTE2 功能描述:Real Time Clock (RTC) IC Clock/Calendar I2C, 2-Wire Serial 8-SOIC (0.154", 3.90mm Width) 制造商:rohm semiconductor 系列:- 包装:剪切带（CT） 零件状态:有效 类型:时钟/日历 特性:警报器，闰年 存储容量:- 时间格式:HH：MM：SS（12/24 小时） 日期格式:YY-MM-DD-dd 接口:I2C，2 线串口 电压 - 电源:1.8 V ~ 5.5 V 电压 - 电源，电池:- 电流 - 计时（最大）:1μA ~ 1.35μA @ 3V ~ 5.5V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商器件封装:* 标准包装:1